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Sintecs Company Presentations

Sintecs Company

Sintecs Applications

Download IBIS Development Studio free version
Download Board Development Studio Trial version
Applications Registration

Sintecs Publications & Articles

AC Termination
Paralell Termination
Series Termination
Thevenin Termination
Sintecs Mentor Graphics Solutions Expo presentation 2010
  • Signal Integrity analysis

    Pre- and post-layout SI and crosstalk analysis

  • Power Integrity analysis

    Current distribution and power plane noise analysis

  • PCB layout

    Extensive knowledge from analog till high–speed digital designs

  • Timing analysis

    Verify the timing constraints of a DDRx interface

  • News

    Sintecs start System on Module development in Dutch press

  • News

    Sintecs launched a new website (press release link will follow soon)

  • News

    System on module press release in Dutch magazine engineers online

  • Events

    Electronics & Automation 2013
    May 28, 29 and 30, 2013

  • Events

    Signal Integrity and High Speed Methodology Training
    November 2, 3 and 4, 2013

  • Events

    Embedded world 2014
    February 25–27, 2014

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Services

  • Signal Integrity analysis
  • PCB layout
  • Thermal analysis
  • Power Integrity analysis
  • Timing analysis
  • DFM/DFA verification
  • EMC verification
  • Library development
  • EDA design support
  • IBIS Resources

Engineering

  • Product design
  • Electronic design
  • Embedded software design
  • FPGA Design
  • Type Approval
  • Application Software Design

Products

  • System on Module
  • SX5
  • Tracy
  • Reference design
  • Product Development Studio
  • Board Development Studio
  • IBIS Development Studio
  • Training

Contacts

+ 31 (0)74 2555 713  
info@sintecs.eu

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