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General conditions

All our deliveries and services are governed by the latest General Conditions of Delivery issued by Federation het Instrument (FHI).

PCB layout

Extensive knowledge from analog till high–speed digital designs
Timing analysis

Verify the timing constraints of a DDRx interface
Power Integrity analysis

Current distribution and power plane noise analysis
Signal Integrity analysis

Pre- and post-layout SI and crosstalk analysis

News

Sintecs start System on Module development in Dutch press
News

Sintecs launched a new website (press release link will follow soon)
News

System on module press release in Dutch magazine engineers online
Events

Electronics & Automation 2013
May 28, 29 and 30, 2013
Events

Signal Integrity and High Speed Methodology Training
November 2, 3 and 4, 2013
Events

Embedded world 2014
February 25–27, 2014

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Signal Integrity analysis
PCB layout
Thermal analysis
Power Integrity analysis
Timing analysis
DFM/DFA verification
EMC verification
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EDA design support
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Product design
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System on Module
SX5
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+ 31 (0)74 2555 713

info@sintecs.eu

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